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Academic Staff

BOLES Steven

B.S., Ph.D.
Assistant Professor

Room: CF608



Dr. Boles currently holds the position of Assistant Professor in the Department of Electrical Engineering at the Hong Kong Polytechnic University. He obtained his B.S. in Materials Science and Engineering from Carnegie Mellon University in 2004. From 2002 to 2005, he was a member of the technical staff at Lumileds Lighting in San Jose, CA. Starting in 2005, he conducted his Ph.D. research at the Massachusetts Institute of Technology in the Department of Materials Science and Engineering. Following his graduation in 2010, he worked as a postdoctoral fellow and research scientist with the Institute for Applied Materials at the Karlsruhe Institute of Technology in Karlsruhe, Germany. In 2014 he joined PolyU as part of strategic effort to bring interdisciplinary expertise in materials science to electrical engineering.

Dr. Boles specializes in the characterization and development of advanced electronic materials for a variety of energy-focused applications. In particular, his research makes use of in-situ and ex-situ electron microscopy to gain basic insight and understanding into the coupled electrical-mechanical response of nanoscale materials under applied stress. He also has interest in developing electrochemical energy storage systems for use in extreme and/or harsh environments.

Honours and Awards

- Alexander-von-Humboldt Postdoctoral Fellowship Award

- Lumileds Lighting Recognition Award

Selected Publications

[1] S. T. Boles, E. A. Fitzgerald, C. V. Thompson, C. K. F. Ho, and K. L. Pey, “Catalyst proximity effects on the growth rate of Si nanowires,” J. Appl. Phys., vol. 106, no. 4, p. 044311, 2009.

[2] S. T. Boles, C. V. Thompson, and E. a. Fitzgerald, “Influence of indium and phosphine on Au-catalyzed InP nanowire growth on Si substrates,” J. Cryst. Growth, vol. 311, no. 5, pp. 1446–1450, 2009.

[3] S.-W. Chang, V. P. Chuang, S. T. Boles, C. A. Ross, and C. V. Thompson, “Densely Packed Arrays of Ultra-High-Aspect-Ratio Silicon Nanowires Fabricated using Block-Copolymer Lithography and Metal-Assisted Etching,” Adv. Funct. Mater., vol. 19, no. 15, pp. 2495–2500, 2009.

[4] O. M. Nayfeh, D. A. Antoniadis, S. T. Boles, C. Ho, and C. V Thompson, “Formation of single tiers of bridging silicon nanowires for transistor applications using vapor-liquid-solid growth from short silicon-on-insulator sidewalls.,” Small, vol. 5, no. 21, pp. 2440–4, 2009.

[5] S. Chang, V. P. Chuang, S. T. Boles, and C. V. Thompson, “Metal-Catalyzed Etching of Vertically Aligned Polysilicon and Amorphous Silicon Nanowire Arrays by Etching Direction Confinement,” Adv. Funct. Mater., vol. 20, no. 24, pp. 4364–4370, 2010.


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